{"id":295,"date":"2013-01-28T11:12:42","date_gmt":"2013-01-28T11:12:42","guid":{"rendered":"https:\/\/staging.speed.pub.ro\/speed3\/?page_id=295"},"modified":"2025-12-11T01:43:27","modified_gmt":"2025-12-10T23:43:27","slug":"mircoprocessor-architecture","status":"publish","type":"page","link":"https:\/\/staging.speed.pub.ro\/speed3\/academic\/microprocessor-architecture\/","title":{"rendered":"Microprocessor Architecture"},"content":{"rendered":"

Course in Bachelor’s program (2nd year, series A, B, F, and G)<\/p>\n

Teachers<\/h3>\n

Prof. Corneliu Burileanu<\/strong><\/a>
\nAssoc. Prof. Horia Cucu<\/a><\/strong>
\nLect. Ana Neac\u0219u<\/strong><\/a>
\nLect. Georgian Nicolae<\/strong><\/a>
\nAs. Andrei D\u0103escu<\/strong><\/a>
\nLect. George-Vl\u0103du\u021b Popescu<\/strong><\/a><\/p>\n

Course Description<\/h3>\n

Study of the basic concepts in CISC and RISC general microprocessor architecture: registers, memory management, addressing techniques, data transfer, instruction set, input\/output strategies. The students should have the possibility to approach any specific microprocessor architecture, either general or dedicated. In the laboratory-type applications, the students are guided in developing applications for the 8086 microprocessor using the emu8086 simulator.<\/p>\n

Contents<\/h3>\n

Course<\/strong><\/p>\n

    \n
  • \u201cMicrocomputer Structure. Defintions\u201d \u2013 Microcomputer Functional Blocks, CISC and RISC Microprocessors, Information in Digital Systems, Conventions<\/li>\n
  • \u201cOverview of a CISC, General Purpose Microprocessor Core\u201d \u2013 First Step Approach: Data register and Address Register, Second Step Approach: General-Purpose Registers, Third Step Approach: Arithmetic Processing Unit, Forth Step Approach: Memory Addressing Control Unit, Fifth Step Approach: Microprocessor Control Unit, Functional Blocks of 16 or 32 bit Microprocessor<\/li>\n
  • \u201cFundamentals of a Typical CISC Architecture\u201d \u2013 Registers, Microcomputer Memory Architecture, Data Transfers, Addressing Techniques, Types of Instructions<\/li>\n
  • \u201cFundamentals of a Typical RISC Architecture\u201d \u2013 Registers, Instruction Set and Addressing Techniques, Microprocessor Control Unit, ARM Microprocessor Family, RISC Advantages and Drawbacks<\/li>\n
  • \u201cInput\/Output Strategies\u201d \u2013 Input\/Output Devices Map, Typical Input\/Output Techniques, Interrupt System for General Purpose Microprocessor, Interrupts for x86 Intel Microprocessor (IA-32) in Real Mode<\/li>\n
  • \u201cTime-Dimension of a General Purpose Microprocessor Architecture\u201d \u2013 CISC Instruction Timing, Speed Increase for Advanced CISC Microprocessor, RISC Instruction Timing<\/li>\n
  • \u201cDesign of a simple processor: CISC vs. RISC\u201d \u2013 Processor Features, Processor Design, Expanding Processor Capabilities<\/li>\n
  • \u201cAn Overview of Intel x86 Architecture (IA-32) in Real Mode\u201d \u2013 Block Diagram, Registers, Memory Organization, Port Organization, Addressing Modes<\/li>\n<\/ul>\n

    Laboratory<\/strong><\/p>\n

      \n
    • Introducing a development environment for x86 microprocessors: emu8086<\/li>\n
    • Data transfer instructions and array operations for x86 microprocessors in real mode<\/li>\n
    • Data processing instructions for x86 microprocessors in real mode<\/li>\n
    • Control program instructions for x86 microprocessors in real mode<\/li>\n
    • Interrupts for x86 microprocessors in real mode<\/li>\n
    • Translation of instructions from high-level programming into assembly<\/li>\n
    • Laboratory assessment<\/li>\n<\/ul>\n

      Grading<\/h3>\n

      Laboratory evaluation (multiple verification tests + optional oral evaluation): 50%
      \nCourse final exam (verification quiz + optional written and oral evaluation): 50%<\/p>\n","protected":false},"excerpt":{"rendered":"

      Course in Bachelor’s program (2nd year, series A, B, F, and G) Teachers Prof. Corneliu Burileanu Assoc. Prof. Horia Cucu Lect. Ana Neac\u0219u Lect. Georgian Nicolae As. Andrei D\u0103escu Lect. George-Vl\u0103du\u021b Popescu Course Description Study of the basic concepts in CISC and RISC general microprocessor architecture: registers, memory management, addressing techniques, data transfer, instruction set,<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":14,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-295","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/pages\/295","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/comments?post=295"}],"version-history":[{"count":74,"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/pages\/295\/revisions"}],"predecessor-version":[{"id":4863,"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/pages\/295\/revisions\/4863"}],"up":[{"embeddable":true,"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/pages\/14"}],"wp:attachment":[{"href":"https:\/\/staging.speed.pub.ro\/speed3\/wp-json\/wp\/v2\/media?parent=295"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}